1. Field of the Invention
The present invention relates to signal generation, and more particularly to generation of signals with profiles or curves guaranteed to envelop or overlap other signals or curves, even when variations of chip processing and operating environments are considered.
2. Background Information
One problem, found in many circuits where transistors are stacked, occurs when one transistor is turning off and the other is turning on. If there is an overlap where both are on, even briefly, relatively large current spikes may occur. These spikes may cause circuit malfunctions.
In many applications there is a continuing need for circuit designs where “break before make” or, possibly, “make before break” operations are required. Ensuring such a sequential operation can relieve the spiking problem and such is an objective of the present invention.
U.S. Pat. No. 6,838,920 B1 ('920), mentioned above, provides a circuit that ensures these sequential operations. This circuit may be used to advantage in many applications. Prior art FIGS. 1 and 2 are taken directly from FIGS. 1 and 2 in '920 patent. An operative feature of the '920 patent is latching that is prominently discussed and claimed therein.
Referring to FIGS. 1 and 2 of the present application, it can be seen that when IN goes high, Q2 turns on and Q1 turns off. Q1 and Q2 are steering FET's that direct the input signal to operate the circuit as discussed. Q1 operates to hold point A high, but Q1 turning off has no effect since the inverter I3 also holds point A high. Point A is also the input to inverter I1, so O2, the output of I1 remains low. Meanwhile, point B, which was high, is driven low by Q2 turning on as IN goes high. Point B is held high by I2 (since O2 remains low), but Q2 is designed to overcome I2's drive and force point B low. When point B goes low, O1 is driven high by I4 with item 20 indicating the initial source of O1 going high is IN going high. When O1 goes high, the latch on point A via I3 is released. Thus, point A goes low and O2 goes high via I1 as indicated by item 22. The feed back around the loops of inverters ensures that O2 goes high well after (by two gate delays at least) and in response to O1 going high. The arrows in FIG. 2 show the imposed sequence of signals, the enveloping is evident.
Correspondingly, when IN goes low, Q1 turns on and Q2 turns off. Q1 drives point A high, but Point B remains low regardless of Q2, since the latching I2 drives B low. Here Q1 overcomes the I3 latch that was driving point A low. Then, in sequence, O2 goes low 24 driving point B high, which drives O1 low 26 via I4. I4, in turn, drives point A high which latches point O1 high. These operations are well shown in the traces shown in FIG. 2.
In each of the above operations, please note that Q2 drives point B low by overcoming the drive of I2; and that Q1 drives point A high overcoming the drive of I3. This contention serves to slow the circuit frequency of operation, affects low voltage operation, dissipates power, and impairs the wave forms/duty cycle of the resulting signals. The present invention is directed to these limitations of the circuit in FIG. 1 and other known prior art circuits, while providing their and other advantages.